Integrated circuits are subjected to rigorous testing to ensure that the resulting integrated circuit (IC) is of high quality. One popular method of testing ICs relies upon a type of fault model called a “stuck-at fault.” The stuck-at (SA) fault model is used by fault simulators and Automatic Test Pattern Generation (ATPG) tools to mimic a manufacturing defect within an IC. The model reflects the behavior of the IC when individual signals or pins are assumed to be stuck at a logical one or a logical zero. In this manner, the SA fault model represents a typical circuit node shorted to power or ground.
SA fault testing involves applying a test pattern to an IC. A “test pattern” refers to a plurality of test vectors, e.g., a set of test vectors, where each test vector is a pattern of logic ones and zeros that can be input to particular ports of the IC. After introducing each test vector into the IC, the behavior of the IC, e.g., outputs, can be observed. For example, if a test vector is introduced into a source of a net, the behavior of the load of that net can be observed to determine whether the load switches or toggles between logic one and zero as expected according to the test vector provided to the source.
The sufficiency of a test pattern in terms of testing an IC can be determined through simulation, e.g., fault simulators and ATPG tools as noted. Each test vector typically tests for a single SA fault. A set of test vectors, therefore, can test for a plurality of different SA faults. The completeness of the test pattern, in terms of detecting SA faults for a particular circuit design, can be rated in terms of a percentage by simulating the circuit design using the test pattern. This percentage can be referred to as the SA fault coverage. For example, a coverage of 99.9% indicates that a test pattern will detect 99.9% of SA faults for a given circuit design.
While SA fault coverage has become a standard upon which the quality of an IC can be judged, the SA fault model is not applicable to all types of faults within an IC. Bridge faults, for example, are a type of fault that is not accurately represented by the SA fault model. Accordingly, while the quality of a test pattern for testing SA faults can be measured, the quality of that same test pattern for testing bridge faults is unknown.